CV

Work

Network Scientist Intern Raytheon BBN

To be determined…

Research Assistant Advanced Networked Systems Research (ANSR) Group, University of Utah

Wireless Association: Researching associations of wireless clients to access points. Developed and implementing algorithm to improve and speed up associations in dense wireless networks. Working with USRP to test new signal processing methods to speed up associations. Researched state of the art wireless protocols 802.11k and 802.11ai.

Network Scientist Intern Raytheon BBN

Worked on DARPA’s Content-Based Mobile Edge Networking (CBMEN) project using Android phones. Improved, measured, and tested the design of the basic ad hoc networking functionality. Thoroughly studied the benefits of using asynchronous I/O compared to synchronous I/O for all network communication. Developed new method for managing multiple TCP connections with neighboring nodes. Built Android application and deployed on 15 devices in the field to measure the improvements. Collaborated closely with three other researchers to improve various components of the system.

Wireless Research Xandem Technology

Researched fall detection and localization using wireless sensor network for elderly care. Led development of small team to implemented real-time room-level localization algorithm using machine learning. Worked with raw wireless data to develop features for machine learning algorithm. Conducted experiments to evaluate and measure the accuracy of localization algorithm. Demonstrated working prototype to potential customers.

Teaching Assistant Software Practice (CS 3500), University of Utah

Helped and taught students basic programming skills in C# such as basic design patterns, testing, debugging, and performance profiling. Worked with groups of students to build large programs involving socket programming, graphical user interfaces, and database storage.

Software Engineering Intern Ancestry.com

Researched an alternative way to store and search terabytes of data using Apache Solr to augment existing database systems. Built the Solr index and ran benchmarks to see how it performed compared to alternative approaches.

Research Assistant Internet Research Lab, Brigham Young University

Contributed to framework, WiFu, for experimenting on wireless transport protocols. Designed new TCP variant protocol specific for wireless mesh networks. Used wireless mesh network to run experiments and benchmark performance of different protocols.

Research Assistant FPGA Lab, Brigham Young University

Helped develop HMFlow framework for rapid prototyping on FPGAs, which uses pre-synthesized hard macro blocks to quickly build designs, 100 times faster than conventional FPGA workflows. Designed and developed fast loading and saving of serialized hard macro blocks. Created complex data structures to model FPGA designs.

Volunteer The Church of Jesus Christ of Latter-day Saints

Worked with groups on goal setting, teaching, and communicating, while resolving conflicts among individuals within these groups. Supported several communities by volunteering at various nonprofit organizations.

Game Tester Amaze Entertainment

Amaze Entertainment provided me with a opportunity to work with real developers and see how teams function at an early age. While working there, I helped to test two games, Lord of the Rings: Tactics and Bionicle Heroes.

Education

University of Utah

  • PhD in Computer Science
  • Studying wireless networks
  • 4.0 / 4.0 GPA

Brigham Young University

  • Bachelors of Science in Computer Engineering
  • Minor in Computer Science
  • 3.89 / 4.0 GPA

Publications

WiFu: A Composable Toolkit for Experimental Wireless Transport Protocols

Extensive research has been performed on improving TCP performance in multi-hop wireless networks, but there have been relatively few experimental evaluations of this work. To make it easier to conduct research in this area, we are releasing WiFu, an open-source toolkit for developing experimental wireless transport protocols. WiFu provides for user-space development of reliable transport and rate control algorithms, greatly simplifying the implementation effort required. In this paper, we describe the architecture of the WiFu toolkit, which decomposes transport protocols into smaller components that enable rapid, plug-and-play development of new variants. We present experiments to demonstrate that the performance of WiFu compares favorably to the Linux kernel for wireless networks. We illustrate the utility of WiFu by using it to conduct experiments with several wireless transport protocols, and show that the performance of some protocols differs significantly from previously reported results.

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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Creating CAD tools for commercial FPGAs is a difficult task. Closed proprietary device databases and unsupported interfaces are largely to blame for the lack of CAD research found on commercial architectures versus hypothetical architectures. This paper formally introduces RapidSmith, a new set of tools and APIs that enable CAD tool creation for Xilinx FPGAs. Based on the Xilinx Design Language (XDL), RapidSmith provides a compact, yet, fast device database with hundreds of APIs that enable the creation of placers, routers and several other tools for Xilinx devices. RapidSmith alleviates several of the difficulties of using XDL and this work demonstrates the kinds of research facilitated by removing such challenges.

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HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

The FPGA compilation process (synthesis, map, place, and route) is a time consuming task that severely limits designer productivity. Compilation time can be reduced by saving implementation data in the form of hard macros. Hard macros consist of previously synthesized, placed and routed circuits that enable rapid design assembly because of the native FPGA circuitry (primitives and nets)which they encapsulate. This work presents results from creating a new FPGA design flow based on hard macros called HMF low. HMF low has shown speedups of 10-50X over the fastest configuration of the Xilinx tools. Designed for rapid prototyping, HMF low achieves these speedups by only utilizing up to 50 percent of the resources on an FPGA and produces implementations that run 2-4X slower than those produced by Xilinx. These speedups are obtained on a wide range of benchmark designs with some exceeding 18,000 slices on a Virtex 4 LX200.

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Rapid prototyping tools for FPGA designs: RapidSmith

Designer productivity for FPGA design is significantly limited by the time-consuming nature of the FPGA compilation process (synthesis, map, placement, and routing). However, experimentation on alternative CAD tools for this purpose for Xilinx devices has been somewhat limited. This paper describes the development and distribution of RapidSmith, a software library to facilitate the manipulation of XDL designs and upon which a complete CAD system can be based. The demonstration portion of this paper will show prototypes of representative CAD tools which can be easily built on top of the RapidSmith system.

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